Power consumption of digital circuitry increases with increasing clock frequency. It is desirable to reduce the clock frequency of a clock used for digital signal processing. Sophisticated electronic components require ever higher data throughput and therefore higher clock frequencies. The highest clock frequency in a system determines the highest possible resolution in time. A timer includes a counter, which is typically a chain of flip-flops that is driven by the system clock. The output of each flip-flop represents a single bit of a binary count representing the timer value. The least significant bit (LSB) toggles with half the frequency of the system clock. The next more significant bit toggles with a quarter of the system clock frequency and so on up to the most significant bit (MSB), which toggles with the lowest frequency. Since power consumption is a function of the clock frequency and of the frequency of state changes of the flip-flops, the maximum power consumption is generated in the LSB flip-flops. In a typical application the actual timer value is only requested from time to time, such as in response to a specific event. The binary count contained in the counter is transferred to a register for timing use. The power consumption consumed by the counter can easily be reduced by reducing the clock frequency. This limits the resolution of the timer and the overall performance of the timer.